1. Field of the Invention
The present invention relates in general to the field of improving the error resilience of memories.
2. Description of the Related Art
In general, data processing systems comprise a processor (often referred to as a central processing unit (CPU)) that executes instructions that are fetched from a main memory. One method to improve the performance of the processor is to use cache memory. Cache memory is high speed memory that works with the processor and the main memory to quickly provide information (e.g., instructions and/or data) to the processor. By using a cache architecture, a faster response time is possible than when the processor fetches all information directly from the main memory. The improved performance is possible because the cache usually contains the information that the processor is likely to request from memory. The cache is typically faster than the main memory; therefore, the cache can usually provide the data required by the processor much faster than the main memory. Part of the methodology used to load information into the cache is to predict and store the information that is frequently used by the processor and is likely to be used by the processor.
When the cache contains information requested by the processor, this is referred to as a cache hit. If the cache does not contain the information requested by the processor, then this is referred to as a cache miss. On a miss, the information is loaded from the main memory into the cache and is also provided to the processor. The information is loaded into the cache in anticipation that the processor will request the data in an upcoming bus cycle. This process continues throughout the operation of the data processing system.
Caches typically include a cache tag array and a cache data array. Each array is organized into a number of cache lines. Each cache line includes a tag portion (contained in the cache tag array) and a storage portion (contained in the cache data array). The tag value in a line is compared with the address of a memory request from the processor to determine whether the requested data is present in the storage portion of that cache line. Validity information is associated with each cache line to indicate whether the line contains currently valid information and whether the information conforms to the information stored within the main memory (referred to as cache coherency). Additionally, for caches which can operate in a copyback or writeback mode, additional status information is retained to indicate whether the cache line is modified (dirty) relative to the value stored in main memory. One example of a protocol for cache coherency is the modified, exclusive, shared, invalid (MESI) protocol.
One issue relating to caches is that with the scaling of technology and power supply, the bit cells are often more sensitive to soft error rates (SER). Another issue relating to caches is that to reduce the standby leakage power, the cache memories are often retained in a low power state during inactive state. This low power state is known to contribute towards increase in SER.